Paging in OS

What is Paging in Operating System?

Paging is a technique that divides memory into fixed-sized blocks. The main memory is divided into blocks known as Frames and the logical memory is divided into blocks known as Pages. Paging requires extra time for the address conversion, so we use a special hardware cache memory known as TLB.

This concept of Paging in OS includes dividing each process in the form of pages of equal size and also, the main memory is divided in the form of frames of fixed size. Now, each page of the process when retrieved into the main memory, is stored in one frame of the memory, and hence, it is also important to have the pages and frames of equal size for mapping and maximum utilization of the memory.

Its main advantage is that the pages can be stored at different locations of the memory and not necessarily in a contiguous manner, though priority is always set to firstly find the contiguous frames for allocating the pages.

If a process has n pages in the secondary memory then there must be n frames available in the main memory for mapping.

Example to understand Paging in OS

CASE-1 (Contiguous Allocation of Pages)

As we can see in the above image, we have main memory divided into 16 frames of the size of 1KB each. Also, there are 4 processes available in the secondary (local) memory: P1, P2, P3, and P4 of a size of 4KB each. Clearly, each process needs to be further subdivided into pages of size of 1KB each, so that one page can be easily mapped to one frame of the main memory. This divides each process into 4 pages and the total for 4 processes gives 16 pages of 1KB each. Initially, all the frames were empty and therefore, pages will be allocated here in a contiguous manner.

CASE-2 (Non-Contiguous Allocation of Pages)

Let us assume that in Case-1, processes P2 and P4 are moved to the waiting state after some time and leave behind the empty space of 8 frames. In Case-2, we have another process P5 of size 8KB (8 pages) waiting inside the ready queue to be allocated. We know that with Paging, we can store the pages at different locations of the memory, and here, we have8non-contiguous frames available. Therefore, we can easily load the 8 pages of the process P5 in the place of P2 and P4 which we can observe in the above image.

Memory Management Unit

MMU is a computer hardware component that responsible for all memory and caching operations which are associated with the CPU. MMU usually exist in CP but in some cases it operates on separate integrated circuit (IC) chip. Here's an overview of how the MMU, specifically in the context of paging, functions in an operating system:

• Virtual Memory Translation: The MMU translates virtual addresses generated by a process into physical addresses in RAM (Random Access Memory). This translation allows processes to run as if they have access to a large, continuous block of memory, even if the physical memory is fragmented or limited.
• Paging: Paging is a memory management scheme where physical memory is divided into fixed-size blocks called "frames," and logical memory is divided into equally sized blocks called "pages." The MMU maps pages to frames, enabling efficient allocation and management of memory.
• Page Tables: The MMU uses page tables to maintain the mapping between virtual pages and physical frames. Each process has its own page table, which keeps track of the virtual-to-physical address translations.
• Page Faults: When a process accesses a page that is not in physical memory, a page fault occurs. The MMU triggers an interrupt, and the operating system must load the required page from secondary storage (usually a hard disk) into a free frame in RAM.
• Page Replacement: If all frames in physical memory are in use, the operating system must choose a page to evict. This process, known as page replacement, is often managed using algorithms like the Least Recently Used (LRU) or the Second Chance algorithm.

Important Features of Paging in PC Reminiscence Management

• Mapping from logical to physical addresses: In the context of paging, the logical address space of a system is divided into fixed-sized pages, with each page associated with a specific physical frame in the main memory. This approach grants the operating system greater flexibility in memory management as it can allocate and release frames as needed.
• Uniform page and frame dimensions: Paging adopts a constant page size, typically matching the size of a frame in the main memory. This simplifies memory management and enhances system efficiency.
• Entries within the page table: Each page within a process's logical address space is represented by a page table entry (PTE) containing details about the corresponding physical frame in the main memory. This information includes the frame number and various control bits used by the operating system for memory management.
• Matching page table entries: The quantity of page table entries in a process's page table is equivalent to the number of pages within the logical address space of the process.
• Page table stored in primary memory: Typically, the page table for each process is stored in the main memory to facilitate efficient access and manipulation by the operating system. However, this approach can introduce some overhead, as the page table must be updated whenever a process is swapped in or out of the main memory.

Advantages of Paging in OS

The advantages of Paging in OS are as follows:

• It is a memory management technique as we can store the pages of a single process in a non-contiguous manner as well which saves the memory.
• The problem of external fragmentation is solved with the help of the Paging technique.
• Allocating the pages within equal and fixed-size frames is easy and simple. Swapping is also easy between the pages and the page frames.

Disadvantages of Paging in OS

The disadvantages of Paging in OS are as follows:

• Internal Fragmentation may occur especially during the allocation of the last page of the process.
• Page tables that are separate for each process in the secondary memory may consume extra memory.
• If we are not using TLB (Translation of look-aside buffer), then the time taken to fetch an instruction and the element byte is high because we need to access the memory two times (for page entry and for actual element within the frame).
• Address translation of logical to physical address lengthens the memory cycle times. Also, it needs specialized hardware.
• Though memory access time can be improved by using TLB, but again there is a limited size of page entries within the TLB up to 1024.